Programmable logic devices (PLDs), such as field programmable gate arrays, programmable interconnect devices, and complex programmable logic devices, are utilized in a wide variety of applications. In general, PLDs and other types of configurable or programmable devices typically employ configuration memory cells, which can be programmed or otherwise store the information that determines the functions or operation of the device. The configuration memory cells may include static random access memory (SRAM) cells (also referred to as SRAM bits), fuses, anti-fuses, or other types of volatile or nonvolatile configuration memory, including one-time programmable devices.
One drawback of certain types of configuration memory cells (e.g., configuration SRAM bits) is their susceptibility to soft errors. Consequently, it would be advantageous to decrease the number of configuration memory cells to decrease the likelihood of a soft error event. For some types of configuration memory cells (e.g., SRAM), an additional advantage that may be obtained by decreasing the number of configuration memory cells is a reduction in the leakage current onto the configuration memory data lines.
For example, multiplexers associated with one or more logic blocks within a PLD may be configured as a number (“N”) of M:1 multiplexers feeding an N:1 multiplexer. This architecture may be configured with N+M SRAM cells, which is a greater number of configuration memory cells than would be required if they were fully decoded (e.g., log2(M*N) configuration memory cells). If the minimum number of configuration memory cells were fully decoded for a large multiplexer, such as for example a 36:1 multiplexer, this would require decoding six bits to provide thirty-six output signals. This approach may have a number of drawbacks, such as requiring multiple stages of decoder logic and a relatively large area to implement the circuitry.
An alternative approach would be to decode fully the minimum number of configuration memory cells (e.g., SRAM bits) required for each multiplexer stage. For example, if a 36:1 multiplexer was implemented by using seven 6:1 multiplexers, then two sets of three SRAM bits would each need to be decoded to provide six output signals (e.g., by employing three input AND gates (NAND followed by an inverter) or three input NOR gates). However, as with the prior approach, a prohibitive amount of die area may be required to implement the circuitry. As a result, there is a need for improved decoding techniques, such as for configuration memory applications or other decoder applications.